This disclosure relates generally to a semiconductor memory device, and, more specifically, to a command decoder that controls internal circuits of a semiconductor chip to operate in synchronism with internal clocks having a pulse width, which is twice as wide as that of an external clock signal.
A conventional command decoder decodes command signals, which are applied from the outside at a rising edge of an external clock signal CLK, such as a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE, to generate a mode setting command MRS, an active command ACTIVE, a precharge command PRECHARGE, a write command WRITE, a read command READ and a refresh command REFRESH. Internal circuits of a semiconductor chip operate according to these commands.
FIG. 1 is a block diagram illustrating a conventional command decoder. FIG. 2 is a timing diagram showing a waveform of signals of the command decoder shown in FIG. 1. Referring to FIG. 1, the command decoder 100 includes a clock generator 110, an input buffer 120 and a latch 130.
The clock generator 100 generates an internal clock signal ICLK having the same pulse width as that of an externally applied clock signal CLK by using the external clock signal CLK. If the external clock signal CLK of 1 GHz (tCK=1 ns) is received, the clock generator 100 generates the internal clock signal ICLK having a High pulse of 500 ps. The input buffer 120 generates an internal command signal CASP using an externally applied column address strobe signal, i.e., external command signal CAS. The latch 130 generates an internal command control signal CASP6, which is synchronized to the internal clock ICLK as shown in FIG. 2, using the internal command signal CASP. The semiconductor chip operates in response to the internal command control signal CASP6.
The command decoder 100, which operates in synchronism with the internal clock signal ICLK having the same pulse width as that of the external clock signal CLK, cannot properly generate a pulse of the internal command control signal CASP6 at a low power supply voltage VDD or high temperature, under which the properties of transistors are poor, because a pulse width of the internal clock signal ICLK is too small. As a result, the semiconductor chip may operate erroneously. In this case, if the current increases for higher speed, the size of the transistor becomes large. Accordingly, there is a problem in that a chip size or the current consumed in the chip is increased.